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- Each storage element is connected to one row and one column selector line.
- Since for every address only one   row and  one column selector line will
  be ``on'', exactly one storage element will have both its row and its column
  selector line ``on''.
- Therefore, a storage element can be selected (or eanbled) by AND-ing  its
  row and its column selector line.
- This suggests that we use a D-flip for a storage element and connect its
  Enable input to the output of the above mentioned AND gate.
- The D-input is connected to the data input line that is common to all
  storage elements.
- Similarly, the output of the flipflop is AND-ed with the output of the
  first AND gate and then connected to a data output line
  that is common to all storage elements.
- This way, only the selected storage element contributes to the common
  output line.
- The final problem arises when data is to be read.
- The read process should leave the value of the gate unchanged.
- To prevent that data is destroyed duing a read operation, a ``write
  enable'' signal is introduced.
- This signal is ``on'' only when new data is to be stored.
- It is AND-ed with the output of the first AND gate and then applied to the  flipflop's Enable input.
- Thus, during read operations (write enable=''off'') the flipflop is
  disabled and does not change its state.
- The write enable signal again is common to all storage elements.
  
Figure 3.16:
Storage Element.
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 Next: Remarks
 Up: Memory ChipsNovember 11, 1998
 Previous: Address Decoder Logic
Prof. Bernd-Peter Paris
1998-12-14