Address Decoder Logic

• The address decoder has a binary number with M bits as its input.
• It has 2^M outputs.
• At any time, only 1 output line is ``on'' and all others are off.
• The line that is ``on'' specifies the desired column or row.
• For M=2, the decoder is shown in the diagram below.
• Notice how the binary representation of the input determines the selected output line.

  

Figure 3.15: Address decoder logic for 2-bit addresses.