D-Flipflop

• An RS-flipflop is rarely used in actual sequential logic.
• However, it is the fundamental building block for the very useful D-flipflop.
• The D-flipflop has only a single data input.
• That data input is connected to the S input of an RS-flip flop, while the inverse of D is connected to the R input.
• This prevents that the input combination ever occurs.
• To allow the flipflop to be in a holding state, a D-flip flop has a second input called ``Enable.''
• The Enable-input is AND-ed with the D-input, such that when Enable=0, the R and S inputs of the RS-flipflop are 0 and the state is held.
• When the Enable-input is 1, the S input of the RS flipflop equals the D input and R is the inverse of D.
• Hence, the value of D determines the value of the output Q when Enable is 1.
• When Enable returns to 0, the most recent input D is ``remembered.''

  

Figure 3.11: D Flip-Flop.